1. Field of Invention
Embodiments of the present invention relate generally to methods of forming semiconductor devices including a buried interconnection line and, more particularly, to methods of forming semiconductor devices including a buried bit line.
2. Description of the Related Art
As semiconductor devices become more highly integrated, transistors included therein shrink in size. Shrinkage of the transistors leads to a reduction of active regions, in size, where the transistors are formed. Accordingly, the transistors of highly integrated semiconductor devices may suffer from a short channel effect and/or a narrow width effect.
A three dimensional transistor such as a vertical transistor has been proposed instead of a conventional planar transistor in order to increase a channel length and/or a channel width in a limited area. Vertical transistors may be very useful to semiconductor memory devices such as dynamic random access memory (DRAM) devices. In a conventional DRAM device employing the vertical transistor as a memory cell transistor, a bit line of the DRAM device may be formed using an ion implantation technique. In this case, there may be a limitation in reducing an electrical resistance of the bit line. Therefore, a method of forming a buried bit line has been proposed to decrease the electrical resistance of the bit line.
In general, buried bit lines may be formed by etching a semiconductor substrate to form a groove and forming a conductive layer on an entire surface of the semiconductor substrate with the groove using a chemical vapor deposition (CVD) technique. The conductive layer may then be etched back to form a pair of separate bit lines on both sidewalls of the groove respectively. The thickness of the conductive layer should be increased in order to decrease the electrical resistance of the bit lines. However, as the integration density of the semiconductor device increases, the width of the groove may be reduced. In this case, there is a limitation in increasing the thickness of the conductive layer. In the event that the thickness of the conductive layer increases, the conductive layer may be formed to have overhangs on upper corners of the groove and the overhangs may be in contact with each other. Therefore, the conductive layer on the bottom surface of the groove may not be removed while the conductive layer is etched back to form the bit lines. This may be due to the presence of the overhangs. As a result, it may be difficult to form a pair of low resistive bit lines, which are electrically isolated from each other, in the narrow groove.